Capacitor Voltage Balancing Strategy Based on SVPWM Technology for Single-Phase Mutil-Level Inverters

doi:10.11985/2017.05.012

Abstract

Abstract:

DC capacitor voltage unbalance causes the distortion of output voltage wave and the degenerate of voltage levels in multi-lever inverters. This issue of single-phase three-level inverter is analyzed and a voltage balancing control strategy based on single-phase SVPWM is proposed. This control strategy realizes the voltage balancing without any auxiliary circuit by choosing switching patterns and deciding their duration appropriately. The reliability and validity of this control strategy have been verified by the simulation results which carried in the Power Simulation environment.

Key words: Voltage balance strategy, multi-level inverter, single-phase SVPWM

CLC Number:

TM464

Yue Guan,Lei Li,He Shi,Aihua Ma. Capacitor Voltage Balancing Strategy Based on SVPWM Technology for Single-Phase Mutil-Level Inverters[J]. Journal of Electrical Engineering, 2017, 12(5): 76-81.

Figures/Tables 11

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电压矢量	U_ab	S_a,S_b
U₀	0	0,0
		1,1
		-1,-1
U₁	U_dc	1,-1
U₂	U_dc/2	1,0
U₂	U_dc/2	0,-1
U₃	-U_dc/2	0,1
U₃	-U_dc/2	-1,0
U₄	-U_dc	-1,1

开关状态	i₁与i_N₁关系	i₁正负
1,0	i₁= -i_N₁	-
0,-1	i₁= i_N₁	+
0,1	i₁= i_N₁	-
-1,0	i₁= -i_N₁	+

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