Journal of Electrical Engineering ›› 2018, Vol. 13 ›› Issue (4): 26-31.doi: 10.11985/2018.04.004

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Research on Common Mode Voltage Suppression Strategy for Two-Level Voltage Inverter

Yang Hao,Lv Xuefeng,Pan Haoming   

  1. State Grid Anhui Electric Power Co.,Ltd. Maintenance Branch Hefei 230061 China
  • Received:2018-01-06 Online:2018-04-25 Published:2019-11-29

Abstract:

In this paper, several methods are introduced, which are mainly divided into two categories of programs, to suppress the common mode voltage (CMV) of inverter. One kind is based on space vector modulation strategy optimization, mainly including the active zero state PWM (AZSPWM), near state PWM (NSPWM), virtual space vector modulation (VSVM) and so on. The other is to change the topology of the hardware circuit to suppress the common mode voltage, which mainly used the three-phase four-leg topology to complete the common mode voltage suppression. In this paper, the simulation and analysis of the above schemes are carried out.

Key words: Inverter, space vector modulation, common mode voltage

CLC Number: